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Si4320
The following receiving frequencies can be set with the different static external pin settings:
PIN16
FCS3
0
0
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
PIN15
FCS2
0
0
0
0
Z
Z
Z
Z
0
0
0
0
Z
Z
Z
Z
PIN10
FCS1
0
0
Z
Z
0
0
Z
Z
0
0
Z
Z
0
0
Z
Z
PIN1
FCS0
0
Z or 1
0
Z or 1
0
Z or 1
0
Z or 1
0
Z or 1
0
Z or 1
0
Z or 1
0
Z or 1
F receiving
PIN2=0
PIN3=0
310.320
310.960
311.600
312.240
312.880
313.520
314.160
314.800
315.440
316.080
316.720
317.360
318.000
318.640
319.280
319.920
F receiving
PIN2=1
PIN3=0
433.360
433.440
433.520
433.600
433.680
433.760
433.840
433.920
434.000
434.080
434.160
434.240
434.320
434.400
434.480
434.560
F receiving
PIN2=0
PIN3=1
(867.680)
(867.840)
(868.000)
868.160
868.320
868.480
868.640
868.800
868.960
869.120
869.280
869.440
869.600
869.760
869.920
(870.080)
F receiving
PIN2=1
PIN3=1
(900.960)
902.880
904.800
906.720
908.640
910.560
912.480
914.400
916.320
918.240
920.160
922.080
924.000
925.920
927.840
(929.760)
Chip Address
Byte
D4h
D2h
B4h
B2h
D4h
D2h
B4h
B2h
D4h
D2h
B4h
B2h
D4h
D2h
B4h
B2h
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Z: Not connected (floating) pin
Values shown as ( italic ) are out-of-band frequencies.
If FCS0=1 (connected to VDD) the RSSI threshold limit is changed from –103 dBm to –97 dBm.
In standalone mode, the operation parameters related to the band, frequency selection and chip address are determined by the
table above. All other control bits (filter bandwidth, bit rate etc.) are determined by the power-on values of the different control
registers.
It is possible to use the receiver in a so-called “mixed mode”. The SPI bus architecture allows access to the bus in standalone
mode (pins 1, 2, 3) and thereby makes it possible to overwrite the default POR values of the control registers. In this way the
operating parameters of the receiver can be programmed over the interface while performing the functions of the standalone
mode when receiving the proper data sequence.
21
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